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september 15, 1999 (version 5.0) 1 features ? high-performance - 5 ns pin-to-pin logic delays on all pins -f cnt to 125 mhz ? large density range - 36 to 288 macrocells with 800 to 6,400 usable gates ? 5 v in-system programmable - endurance of 10,000 program/erase cycles - program/erase over full commercial voltage and temperature range ? enhanced pin-locking architecture ? flexible 36v18 function block - 90 product terms drive any or all of 18 macrocells within function block - global and product term clocks, output enables, set and reset signals ? extensive ieee std 1149.1 boundary-scan (jtag) support ? programmable power reduction mode in each macrocell ? slew rate control on individual outputs ? user programmable ground pin capability ? extended pattern security features for design protection ? high-drive 24 ma outputs ? 3.3 v or 5 v i/o capability ? advanced cmos 5v fastflash technology ? supports parallel programming of multiple xc9500 devices family overview the xc9500 cpld family provides advanced in-system programming and test capabilities for high performance, general purpose logic integration. all devices are in-system programmable for a minimum of 10,000 program/erase cycles. extensive ieee 1149.1 (jtag) boundary-scan sup- port is also included on all family members. as shown in table 1 , logic density of the xc9500 devices ranges from 800 to over 6,400 usable gates with 36 to 288 registers, respectively. multiple package options and asso- ciated i/o capacity are shown in ta b l e 2 . the xc9500 fam- ily is fully pin-compatible allowing easy design migration across multiple density options in a given package foot- print. the xc9500 architectural features address the require- ments of in-system programmability. enhanced pin-locking capability avoids costly board rework. an expanded jtag instruction set allows version control of programming pat- terns and in-system debugging. in-system programming throughout the full device operating range and a minimum of 10,000 program/erase cycles provide worry-free recon- figurations and system field upgrades. advanced system features include output slew rate control and user-programmable ground pins to help reduce system noise. i/os may be configured for 3.3 v or 5 v operation. all outputs provide 24 ma drive. architecture description each xc9500 device is a subsystem consisting of multiple function blocks (fbs) and i/o blocks (iobs) fully intercon- nected by the fastconnect switch matrix. the iob pro- vides buffering for device inputs and outputs. each fb provides programmable logic capability with 36 inputs and 18 outputs. the fastconnect switch matrix connects all fb outputs and input signals to the fb inputs. for each fb, 12 to 18 outputs (depending on package pin-count) and associated output enable signals drive directly to the iobs. see figure 1 . 0 xc9500 in-system programmable cpld family september 15, 1999 (version 5.0) 01* r
r xc9500 in-system programmable cpld family 2 september 15, 1999 (version 5.0) table 1: xc9500 device family note: f cnt = operating frequency for 16-bit counters f system = internal operating frequency for general purpose system designs spanning multiple fbs. figure 1: xc9500 architecture note: function block outputs (indicated by the bold line) drive the i/o blocks directly. in-system programming controller jtag controller i/o blocks function block 1 macrocells 1 to 18 macrocells 1 to 18 macrocells 1 to 18 macrocells 1 to 18 jtag port 3 36 i/o/gts i/o/gsr i/o/gck i/o i/o i/o i/o 2 or 4 1 i/o i/o i/o i/o 3 x5877 function block 2 36 function block 3 36 18 18 18 18 function block n 36 fastconnect switch matrix xc9536 xc9572 xc95108 xc95144 xc95216 xc95288 macrocells 36 72 108 144 216 288 usable gates 800 1,600 2,400 3,200 4,800 6,400 registers 36 72 108 144 216 288 t pd (ns) 5 7.5 7.5 7.5 10 10 t su (ns) 3.5 4.5 4.5 4.5 6.0 6.0 t co (ns) 4.0 4.5 4.5 4.5 6.0 6.0 f cnt (mhz) 100 125 125 125 111.1 111.1 f system (mhz) 100 83.3 83.3 83.3 66.7 66.7
r september 15, 1999 (version 5.0) 3 xc9500 in-system programmable cpld family 5 function block each function block, as shown in figure 2 , is comprised of 18 independent macrocells, each capable of implementing a combinatorial or registered function. the fb also receives global clock, output enable, and set/reset signals. the fb generates 18 outputs that drive the fastconnect switch matrix. these 18 outputs and their corresponding output enable signals also drive the iob. logic within the fb is implemented using a sum-of-prod- ucts representation. thirty-six inputs provide 72 true and complement signals into the programmable and-array to form 90 product terms. any number of these product terms, up to the 90 available, can be allocated to each macrocell by the product term allocator. each fb (except for the xc9536) supports local feedback paths that allow any number of fb outputs to drive into its own programmable and-array without going outside the fb. these paths are used for creating very fast counters and state machines where all state registers are within the same fb. table 2: available packages and device i/o pins (not including dedicated jtag pins) xc9536 xc9572 xc95108 xc95144 xc95216 xc95288 44-pin vqfp 34 44-pin plcc 34 34 48-pin csp 34 84-pin plcc 69 69 100-pin tqfp 72 81 81 100-pin pqfp 72 81 81 160-pin pqfp 108 133 133 208-pin hqfp 166 168 352-pin bga 166 192 figure 2: xc9500 function block macrocell 18 macrocell 1 programmable and-array product term allocators from fastconnect switch matrix x5878 36 1 to fastconnect switch matrix to i/o blocks out global set/reset 3 18 ptoe 18 18 global clocks
r xc9500 in-system programmable cpld family 4 september 15, 1999 (version 5.0) macrocell each xc9500 macrocell may be individually configured for a combinatorial or registered function. the macrocell and associated fb logic is shown in figure 3 . five direct product terms from the and-array are available for use as primary data inputs (to the or and xor gates) to implement combinatorial functions, or as control inputs including clock, set/reset, and output enable. the product term allocator associated with each macrocell selects how the five direct terms are used. the macrocell register can be configured as a d-type or t-type flip-flop, or it may be bypassed for combinatorial operation. each register supports both asynchronous set and reset operations. during power-up, all user registers are initialized to the user-defined preload state (default to 0 if unspecified). x5879 to fastconnect switch matrix additional product terms (from other macrocells) global set/reset global clocks additional product terms (from other macrocells) to i/o blocks out 1 0 36 3 ptoe d/t q s r product term allocator product term set product term clock product term reset product term oe figure 3: xc9500 marcocell within function block
r september 15, 1999 (version 5.0) 5 xc9500 in-system programmable cpld family 5 d/t s r macrocell x5880 i/o/gsr product term set product term clock product term reset global set/reset global clock 1 global clock 2 global clock 3 i/o/gck1 i/o/gck2 i/o/gck3 all global control signals are available to each individual macrocell, including clock, set/reset, and output enable sig- nals. as shown in figure 4 , the macrocell register clock originates from either of three global clocks or a product term clock. both true and complement polarities of a gck pin can be used within the device. a gsr input is also pro- vided to allow user registers to be set to a user-defined state. figure 4: macrocell clock and set/reset capability
r xc9500 in-system programmable cpld family 6 september 15, 1999 (version 5.0) product term allocator the product term allocator controls how the five direct product terms are assigned to each macrocell. for exam- ple, all five direct terms can drive the or function as shown in figure 5 . the product term allocator can re-assign other product terms within the fb to increase the logic capacity of a mac- rocell beyond five direct terms. any macrocell requiring additional product terms can access uncommitted product terms in other macrocells within the fb. up to 15 product terms can be available to a single macrocell with only a small incremental delay of t pta , as shown in figure 6 . note that the incremental delay affects only the product terms in other macrocells. the timing of the direct product terms is not changed. figure 5: macrocell logic using direct product term macrocell product term logic product term allocator x5894 figure 6: product term allocation with 15 product terms macrocell logic with 15 p-terms product term allocator product term allocator x5895 product term allocator
r september 15, 1999 (version 5.0) 7 xc9500 in-system programmable cpld family 5 the product term allocator can re-assign product terms from any macrocell within the fb by combining partial sums of products over several macrocells, as shown in figure 7 . in this example, the incremental delay is only 2 * t pta . all 90 product terms are available to any macrocell, with a maxi- mum incremental delay of 8 * t pta . figure 7: product term allocation over several macrocells macrocell logic with 18 product terms macrocell logic with 2 product terms product term allocator product term allocator x5896 product term allocator product term allocator
r xc9500 in-system programmable cpld family 8 september 15, 1999 (version 5.0) the internal logic of the product term allocator is shown in figure 8 . figure 8: product term allocator logic d/t q s r from upper macrocell to upper macrocell product term set product term clock product term reset global set/reset global set/reset global clocks product term oe product term allocator to lower macrocell from lower macrocell x5881 1 0
r september 15, 1999 (version 5.0) 9 xc9500 in-system programmable cpld family 5 fastconnect switch matrix the fastconnect switch matrix connects signals to the fb inputs, as shown in figure 9 . all iob outputs (corre- sponding to user pin inputs) and all fb outputs drive the fastconnect matrix. any of these (up to a fb fan-in limit of 36) may be selected, through user programming, to drive each fb with a uniform delay. the fastconnect switch matrix is capable of combining multiple internal connections into a single wired-and out- put before driving the destination fb. this provides addi- tional logic capability and increases the effective logic fan-in of the destination fb without any additional timing delay. this capability is available for internal connections originating from fb outputs only. it is automatically invoked by the development software where applicable. 99021101 function block fastconnect switch matrix (36) i/o function block i/o block 18 18 i/o block (36) i/o d/t q d/t q wired-and capability figure 9: fastconnect switch matrix
r xc9500 in-system programmable cpld family 10 september 15, 1999 (version 5.0) i/o block the i/o block (iob) interfaces between the internal logic and the device user i/o pins. each iob includes an input buffer, output driver, output enable selection multiplexer, and user programmable ground control. see figure 10 for details. the input buffer is compatible with standard 5 v cmos, 5 v ttl and 3.3 v signal levels. the input buffer uses the internal 5 v voltage supply (v ccint ) to ensure that the input thresh- olds are constant and do not vary with the v ccio voltage. the output enable may be generated from one of four options: a product term signal from the macrocell, any of the global oe signals, always 1, or always 0. there are two global output enables for devices with up to 144 mac- rocells, and four global output enables for devices with 180 or more macrocells. both polarities of any of the global 3-state control (gts) pins may be used within the device. figure 10: i/o block and output enable capability i/o block macrocell x5899_01 product term oe ptoe switch matrix out (inversion in and-array) global oe 1 1 to other macrocells v ccint slew rate control 0 global oe 2 available in xc95216 and xc95288 global oe 3 global oe 4 i/o/gts1 i/o i/o/gts2 i/o/gts3 i/o/gts4 to fastconnect user- programmable ground pull-up resistor v ccio * * pull-up resistors are used to prevent floating pins during programming and other times. they are disabled during normal operations.
r september 15, 1999 (version 5.0) 11 xc9500 in-system programmable cpld family 5 each output has independent slew rate control. output edge rates may be slowed down to reduce system noise (with an additional time delay of t slew ) through program- ming. see figure 11 . each iob provides user programmable ground pin capabil- ity. this allows device i/o pins to be configured as addi- tional ground pins. by tying strategically located programmable ground pins to the external ground connec- tion, system noise generated from large numbers of simul- taneous switching outputs may be reduced. a control pull-up resistor (typically 10k ohms) is attached to each device i/o pin to prevent them from floating when the device is not in normal user operation. this resistor is active during device programming mode and system power-up. it is also activated for an erased device. the resistor is deactivated during normal operation. the output driver is capable of supplying 24 ma output drive. all output drivers in the device may be configured for either 5 v ttl levels or 3.3 v levels by connecting the device output voltage supply (v ccio ) to a 5 v or 3.3 v voltage supply. figure 12 shows how the xc9500 device can be used in 5 v only and mixed 3.3 v/5 v systems. pin-locking capability the capability to lock the user defined pin assignments dur- ing design changes depends on the ability of the architec- ture to adapt to unexpected changes. the xc9500 devices have architectural features that enhance the ability to accept design changes while maintaining the same pinout. the xc9500 architecture provides maximum routing within the fastconnect switch matrix, and incorporates a flexi- ble function block that allows block-wide allocation of available product terms. this provides a high level of confi- dence of maintaining both input and output pin assign- ments for unexpected design changes. for extensive design changes requiring higher logic capac- ity than is available in the initially chosen device, the new design may be able to fit into a larger pin-compatible device using the same pin assignments. the same board may be used with a higher density device without the expense of board rework. time 0 0 1 .5 v standard output voltage (a) slew-rated limited t slew time 1.5 v output voltage (b) t slew standard slew-rated limited x5900 figure 11: output slew-rate for (a) rising and (b) falling outputs figure 12: xc9500 devices in (a) 5 v systems and (b) mixed 3.3 v/5 v systems in out xc9500 cpld v ccint v ccio 5 v 5 v cmos 5 v or or 0 v 3.3 v gnd (b) x5901 5 v ttl 3.6 v 0 v 3.3 v 3.3 v 0 v 3.3 v 3.3 v 0 v in out xc9500 cpld v ccint v ccio 5 v 5 v cmos 5 v or or 0 v gnd (a) 5 v ttl 3.6 v 0 v 3.3 v 3.3 v 0 v 5 v ttl ~ 4 v 0 v
r xc9500 in-system programmable cpld family 12 september 15, 1999 (version 5.0) in-system programming xc9500 devices are programmed in-system via a standard 4-pin jtag protocol, as shown in figure 13 . in-system pro- gramming offers quick and efficient design iterations and eliminates package handling. the xilinx development sys- tem provides the programming data sequence using a xil- inx download cable, a third-party jtag development system, jtag-compatible board tester, or a simple micro- processor interface that emulates the jtag instruction sequence. all i/os are 3-stated and pulled high by the iob resistors during in-system programming. if a particular signal must remain low during this time, then a pulldown resistor may be added to the pin. external programming xc9500 devices can also be programmed by the xilinx hw130 device programmer as well as third-party program- mers. this provides the added flexibility of using pre-pro- grammed devices during manufacturing, with an in-system programmable option for future enhancements. endurance all xc9500 cplds provide a minimum endurance level of 10,000 in-system program/erase cycles. each device meets all functional, performance, and data retention spec- ifications within this endurance limit. ieee 1149.1 boundary-scan (jtag) xc9500 devices fully support ieee 1149.1 boundary-scan (jtag). extest, sample/preload, bypass, user- code, intest, idcode, and highz instructions are sup- ported in each device. for isp operations, five additional instructions are added; the ispen, ferase, fpgm, fvfy, and ispex instructions are fully compliant exten- sions of the 1149.1 instruction set. the tms and tck pins have dedicated pull-up resistors as specified by the ieee 1149.1 standard. boundary scan description language (bsdl) files for the xc9500 are included in the development system and are available on the xilinx ftp site. design security xc9500 devices incorporate advanced data security fea- tures which fully protect the programming data against unauthorized reading or inadvertent device erasure/repro- gramming. table 3 shows the four different security set- tings available. the read security bits can be set by the user to prevent the internal programming pattern from being read or copied. when set, they also inhibit further program operations but allow device erase. erasing the entire device is the only way to reset the read security bit. the write security bits provide added protection against accidental device erasure or reprogramming when the jtag pins are subject to noise, such as during system power-up. once set, the write-protection may be deacti- vated when the device needs to be reprogrammed with a valid pattern. table 3: data security options default default read allowed read security program/erase allowed read inhibited program inhibited/erase allowed read allowed program/erase inhibited read inhibited program/erase inhibited set set write security x5905
r september 15, 1999 (version 5.0) 13 xc9500 in-system programmable cpld family 5 low power mode all xc9500 devices offer a low-power mode for individual macrocells or across all macrocells. this feature allows the device power to be significantly reduced. each individual macrocell may be programmed in low-power mode by the user. performance-critical parts of the application can remain in standard power mode, while other parts of the application may be programmed for low-power operation to reduce the overall power dissipa- tion. macrocells programmed for low-power mode incur additional delay (t lp ) in pin-to-pin combinatorial delay as well as register setup time. product term clock to output and product term output enable delays are unaffected by the macrocell power-setting. timing model the uniformity of the xc9500 architecture allows a simpli- fied timing model for the entire device. the basic timing model, shown in figure 14 , is valid for macrocell functions that use the direct product terms only, with standard power setting, and standard slew rate setting. table 4 shows how each of the key timing parameters is affected by the prod- uct term allocator (if needed), low-power setting, and slew-limited setting. the product term allocation time depends on the logic span of the macrocell function, which is defined as one less than the maximum number of allocators in the product term path. if only direct product terms are used, then the logic span is 0. the example in figure 6 shows that up to 15 product terms are available with a span of 1. in the case of figure 7 , the 18 product term function has a span of 2. detailed timing information may be derived from the full timing model shown in figure 15 . the values and explana- tions for each parameter are given in the individual device data sheets. figure 13: in-system programming operation (a) solder device to pcb and (b) program using download cable x5902 g n d v cc (a) (b)
r xc9500 in-system programmable cpld family 14 september 15, 1999 (version 5.0) figure 15: detailed timing model power-up characteristics the xc9500 devices are well behaved under all operating conditions. during power-up each xc9500 device employs internal circuitry which keeps the device in the quiescent state until the v ccint supply voltage is at a safe level (approximately 3.8 v). during this time, all device pins and jtag pins are disabled and all device outputs are disabled with the iob pull-up resistors (~ 10k ohms) enabled, as shown in table 5 . when the supply voltage reaches a safe level, all user registers become initialized (typically within 100 m s for 9536 - 95144, 200 m s for 95216 and 300 m s for 95288), and the device is immediately available for opera- tion, as shown in figure 16 . combinatorial logic propagation delay = t pd (a) combinatorial logic setup time = t su t su t psu t pco t co clock to out time = t co (b) d/t q combinatorial logic internal system cycle time = t system (d) d/t q combinatorial logic combinatorial logic propagation delay = t pd + t fbk with feedback (f) combinatorial logic combinatorial logic all resources within fb using local feedback setup time internal cycle time = t cnt (e) d/t q combinatorial logic setup time = t psu clock to out time = t pco (c) p-term clock path d/t q figure 14: basic timing model s*t pta t ptsr t pdi t sui t hi t coi t aoi t rai d/t q sr > t in t gck t gsr t gts t logilp t logi t ptck t ptts t lf t out t slew t en t f pin feedback
r september 15, 1999 (version 5.0) 15 xc9500 in-system programmable cpld family 5 if the device is in the erased state (before any user pattern is programmed), the device outputs remain disabled with the iob pull-up resistors enabled. the jtag pins are enabled to allow the device to be programmed at any time. if the device is programmed, the device inputs and outputs take on their configured states for normal operation. the jtag pins are enabled to allow device erasure or bound- ary-scan tests at any time. development system support the xc9500 cpld family is fully supported by the develop- ment systems available from xilinx and the xilinx alliance program vendors. the designer can create the design using abel, schemat- ics, equations, vhdl, or verilog in a variety of software front-end tools. the development system can be used to implement the design and generate a jedec bitmap which can be used to program the xc9500 device. each develop- ment system includes jtag download software that can be used to program the devices via the standard jtag inter- face and a download cable. fastflash technology an advanced cmos flash process is used to fabricate all xc9500 devices. specifically developed for xilinx in-system pro- grammable cplds, the fastflash process provides high performance logic capability, fast programming times, and endurance of 10,000 program/erase cycles. note: 1. s = the logic span of the function, as defined in the text. figure 16: device behavior during power-up v ccint no power 3.8 v (typ) 0 v no power quiescent state quiescent state user operation initialization of user registers x5904 table 4: timing model parameters description parameter product term allocator 1 macrocell low-power setting output slew-limited setting propagation delay t pd + t pta * s+ t lp + t slew global clock setup time t su + t pta * s+ t lp C global clock-to-output t co CC+ t slew product term clock setup time t psu + t pta * s+ t lp C product term clock-to-output t pco CC+ t slew internal system cycle period t system + t pta * s+ t lp C table 5: xc9500 device characteristics device circuitry quiescent state erased device operation valid user operation iob pull-up resistors enabled enabled disabled device outputs disabled disabled as configured device inputs and clocks disabled disabled as configured function block disabled disabled as configured jtag controller disabled enabled enabled
r xc9500 in-system programmable cpld family 16 september 15, 1999 (version 5.0) revision history version date revision 3.0 12/14/98 revised datasheet to reflect new ac characteristics and internal timing parmeters. 4.0 2/10/99 corrected figure 3 5.0 9/15/99 added -10 speed grade to 95288

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